In a communications base station, both a receive channel and a feedback channel generally require a high-speed and high-precision analog-to-digital converter (ADC, Analog-Digital Converter). A pipeline ADC is one of various existing ADC architectures.
In consideration of noise, power consumption, design difficulty, and the like, existing pipeline ADCs are increasingly prone to employ a structure without a sample-and-hold stage. As shown in FIG. 1, taking a stage 0 pipeline for example, it means that a sub-digital-to-analog converter (MDAC0) and a sub-analog-to-digital converter (subADC0) that serve as sampling channels (where 0 indicates the stage 0 pipeline of the pipeline analog-to-digital converter) both need to deal with high-frequency and large-swing input signals, which imposes a higher requirement on a core module—a comparator in the subADC0.
Currently, a comparator used in the subADC0 is shown in FIG. 2. In the comparator, a switch 511, a switch S12, a switch S13, a switch S14, a switch S15, and a switch S16 are controlled by a clock signal CLK1; and a switch 521, a switch 522, and a switch S23 are controlled by a clock signal CLK2. When the clock signal CLK1 controls the switches S11-516 to close, the clock signal CLK2 controls the switches S21-S23 to open; when the clock signal CLK1 controls the switches S11-516 to open, the clock signal CLK2 controls the switches S21-S23 to close. The comparator has a total of two working phases: a sampling phase and a comparing phase. In the comparing phase, the switches S21-S23 are closed, a capacitor CS1 collects a negative reference signal Vrefn to one polar plate of the capacitor CS1, and a capacitor CS2 collects a postive reference signal Vrefp to one polar plate of the capacitor CS2. In this case, an equivalent circuit diagram of the comparator in FIG. 2 is shown in FIG. 3. In the sampling phase, the switches S11-S16 are closed. In this case, the capacitor CS1 and the capacitor CS2 work as coupled capacitors. The capacitor CS1 subtracts a value of a negative reference signal Vrefn, which is collected in a previous comparing phase of the sampling phase, from a value of a positive input signal Vip, and transmits a signal obtained after the subtraction to a capacitor Cf1 along an input signal path 1 indicated by a dashed line in FIG. 2. The capacitor CS2 subtracts a value of a positive reference signal Vrefp, which is collected in a previous comparing phase of the sampling phase, from a value of a negative input signal Vin, and transmits a signal obtained after the subtraction to a capacitor Cf2 along an input signal path 2 indicated by a dashed line in FIG. 2. In this case, an equivalent circuit diagram of the comparator in FIG. 2 is shown in FIG. 4, where a field effect transistor M8 and a field effect transistor M10 form a phase inverter Inv3, and a field effect transistor M9 and a field effect transistor M11 form a phase inverter Inv4. In a next comparing phase of the sampling phase, the switches S21-S23 are closed, the phase inverter formed by the field effect transistor M8 and the field effect transistor M10 is coupled with the phase inverter formed by the field effect transistor M9 and the field effect transistor M11 through the capacitor Cf1 and the capacitor Cf2, thereby forming positive feedback. An equivalent circuit diagram of the comparator in FIG. 2 is shown in FIG. 5, where a capacitor Cpar8 is a gate parasitic capacitor of the field effect transistor M8 and is contained in the field effect transistor M8; a capacitor Cpar9 is a gate parasitic capacitor of the field effect transistor M9 and is contained in the field effect transistor M9; a capacitor Cpar10 is a gate parasitic capacitor of the field effect transistor M10 and is contained in the field effect transistor M10; and a capacitor Cpar11 is a gate parasitic capacitor of the field effect transistor M11 and is contained in the field effect transistor M11. In the comparator shown in FIG. 2, a source of a field effect transistor M6 is connected to a VDD, and a drain of the field effect transistor M6 is connected to a current source; and a source of a field effect transistor M7 is connected to the VDD, and a drain of the field effect transistor M7 is connected to the current source.
As shown in FIG. 5, in the comparing phase, a latch formed by the field effect transistor M8, the field effect transistor M9, the field effect transistor M10, and the field effect transistor M11 drives gates of the field effect transistors through the capacitor Cf1 and the capacitor Cf2. However, a gate of each field effect transistor has a parasitic capacitor. Therefore, when a signal sampled on the capacitor Cf1 drives the field effect transistor M9 and the field effect transistor M11, voltage is divided by the gate parasitic capacitor Cpar9 of the field effect transistor M9 and the gate parasitic capacitor Cpar11 of the field effect transistor M11, thereby weakening a driving capability of the latch and reducing a comparing speed.
To sum up, when the foregoing comparator structure is used, a comparator samples a signal to a sampling capacitor (that is, the capacitor Cf1 and the capacitor Cf2) during signal sampling; in a comparing phase, because a gate of each field effect transistor in a latch of the comparator has a parasitic capacitor, when the signal on the sampling capacitor drives the field effect transistor, the parasitic capacitor produces a voltage dividing effect, thereby weakening a driving capability and reducing a comparing speed.